Chip stacking with TSV technology has been of interest in recent years. In the chip stacking process, the wafer needs be thinned down to 50 μm-200 μm thick for 300 mm Si wafers. However, the coefficient of thermal expansion (CTE) mismatch of different films and temperature cycles during semiconductor processing cause significant wafer bowing, which becomes more significant for thin wafers. That is, CTE mismatch between film and substrate causes significant wafer bowing during process (thermal cycle). Handling and processing thin wafers then becomes extremely challenging.